This invention generally relates to integrated circuits having charge-recycling stacked voltage domains. More specifically, the invention relates to calibration schemes for such stacked voltage domains.
In the design and operation of integrated circuits, power consumption is a major concern. As a result of the devices on the circuits becoming smaller and of the higher performance requirements for the circuits, the circuits, or chips, are consuming more power, and the voltage levels supplied to the circuits are being reduced. This leads to a significant growth in the currents needed to operate the devices on the circuits.
In on-chip and inter-chip data communication systems where high data bandwidth is required, power dissipation and I/O area are very crucial. For instance, in modern multi-core microprocessors, processor cores and caches are connected by data buses having thousands of bits. In high-performance servers, the inter-chip links from processors to network switches or off-chip cache also require I/O buses hundreds of bits wide running at multiple Gb/s per lane data rates. Compact and low-power I/O schemes are needed for these high-performance systems. Among various circuit blocks in an I/O system, the signaling power dissipated on the channel consumes a big part of the overall I/O power. Since the signaling power is proportional to the square of the voltage swing transmitted on the channel, it is well known that reducing the signal swing will lower the signaling power.
Charge-recycling techniques have been presented to achieve reduced signal swing by stacking circuits with regular and predictable data switching activities, such as logic circuits [S. Rajapandian et al., “High-Voltage Power Delivery Through Charge Recycling”, JSSC, pp. 1400-1410, June 2006] or clocking circuits [R. Inti et al., “Intergraded Regulation for Energy-Efficient Digital Circuits”, ISSCC, pp. 152-153, February 2011]. Charge-recycling stacked low-swing I/O is also disclosed in U.S. Patent Application Publication No. 2011/0298440, the disclosure of which is hereby incorporated herein by reference. In charge-recycling stacked logic domains, two groups of drivers are logically stacked between the supply voltage and ground.
Since the voltage regulator provides regulation function only when there is current mismatch between the top and bottom driver groups, the on-chip voltage regulator can be very compact and highly efficient. Due to its high area and power efficiency, the charge-recycling stacked I/O scheme can be well suited for a variety of applications, including on-chip signaling, across-chip signaling in 3D chip stack and local chip-to-chip signaling through silicon carrier or other benign channels.
However, the I/O performance can be adversely affected due to chip process variations, supply voltage fluctuations and temperature deviations along the I/O bus. The charge-recycling stacked I/O should be robust against PVT variations, i.e., process, voltage and temperature variations. Appropriate calibration approaches are needed to achieve this robust I/O performance over different operating conditions.